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PRODUCT INFO
SCANPSC100FSC by FAIRCHILD
Image is representational - see manufacturer’s specifications
FAIRCHILD

SCANPSC100FSC

Fairchild

Embedded Boundary Scan Controller (Ieee 1149.1 Support)

PRICING per each  AVAILABILITY real time   
1-24 :$24.90
25-99 :$23.95
100-249 :$21.40
250-499 :$21.30
500 + :$20.91
291 can ship tomorrow
In our stock 
Ships From: Phoenix, AZ
12 views in the last month Popularity 
RESOURCES
SPECS
Supplier: Fairchild
Part No: SCANPSC100FSC
RoHS: Yes
Supplier Standard Pack: This information is provided for customers who prefer to buy in multiples of the Manufacturer’s Standard Package quantity. <b>Minimum Order Quantities</b> and <b>Required Order Multiples</b> are presented with our price and availability information. 26
Family: SCANPSC100F
Supplier_Package: SOIC W
Pin_Count: 28
Dimension: 17.9 x 7.5 x 2.35(Max) mm
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DESCRIPTION
The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus. It is useful in improving scan throughput when applying serial vectors to system test circuitry and reduces the software overhead that is associated with applying serial patterns with a parallel processor. The SCANPSC100F operates by serializing data from the parallel bus for shifting through the chain of 1149.1 compliant components (i.e., scan chain). Scan data returning from the scan chain is placed on the parallel port to be read by the host processor. Up to two scan chains can be directly controlled with the SCANPSC100F via two independent TMS pins. Scan control is supplied with user specific patterns which makes the SCANPSC100F protocol-independent. Overflow and underflow conditions are prevented by stopping the test clock

Product Highlights
  • Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture
  • Supported by Fairchild's SCAN Ease (Embedded Application Software Enabler) Software
  • Uses generic, asynchronous processor interface; compatible with a wide range of processors and PCLK frequencies
  • Directly supports up to two 1149.1 scan chains
  • 16-bit Serial Signature Compaction (SSC) at the Test Data In (TDI) port
  • Automatically produces pseudo-random patterns at the Test Data Out (TDO) port
  • Fabricated on FACT™ 1.5 µm CMOS process
  • Supports 1149.1 test clock (TCK) frequencies up to 25 MHz
  • TTL-compatible inputs; full-swing CMOS outputs with 24 mA source/sink capability
COMMUNITY FORUM
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PART CLASSIFICATION DATA
HTS: 8542390000
ECCN: EAR99
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