DM74ALS138M FAIRCHILD | Decoder & Demux
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PRODUCT INFO
DM74ALS138M by FAIRCHILD
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FAIRCHILD

DM74ALS138M

Fairchild

Decoder/Demultiplexer Single 3-to-8 16-Pin SOIC N Rail

PRICING per each  AVAILABILITY Updated Today   
1-2,499 :$0.403
2,500 + :$0.383
299 can ship today
In our stock This is the quantity we have on-hand in our inventory for immediate shipment.
Ships From: Phoenix, AZ
In Stock quantities placed in the next
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RESOURCES
SPECS
Supplier: Fairchild
Part No: DM74ALS138M
RoHS: Yes
Supplier Standard Pack: This information is provided for customers who prefer to buy in multiples of the Manufacturer’s Standard Package quantity. <b>Minimum Order Quantities</b> and <b>Required Order Multiples</b> are presented with our price and availability information. 960
Maximum Low Level Output Current: 8 mA
Logic Function: Decoder/Demultiplexer
Minimum Operating Supply Voltage: 4.5 V
Output Type: N/A
Family: DM74ALS138
Polarity: Inverting
Supplier_Package: SOIC N
Packaging: Rail
Logic Family: ALS
Pin_Count: 16
Mounting: Surface Mount
Maximum High Level Output Current: -0.4 mA
Number of Elements per Chip: 1
Maximum Operating Supply Voltage: 5.5 V
Typical Operating Supply Voltage: 5 V
Operating Temperature: 0 to 70 °C
Dimension: 10(Max) x 4(Max) x 1.5(Max) mm
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DESCRIPTION
These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The DM74ALS138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs. Two active-LOW and one active-HIGH enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications

Product Highlights
  • Designed specifically for high speed:

    Memory decoders

    Data transmission systems

  • 3- to 8-line decoder incorporates 3 enable inputs to simplify cascading and/or data reception
  • Low power dissipationDz3 mW typ
  • Switching specifications guaranteed over full temperature and VCC range
  • Advanced oxide-isolated, ion-implanted Schottky TTL process
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PART CLASSIFICATION DATA
HTS: 8542390000
ECCN: EAR99