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Flip Flop JK-Type Neg-Edge 2-Element 16-Pin PDIP W Rail
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Maximum Low Level Output Current:
Minimum Operating Supply Voltage:
Number of Channels per Chip:
Maximum High Level Output Current:
Number of Elements per Chip:
Maximum Operating Supply Voltage:
Typical Operating Supply Voltage:
0 to 70 °C
19.68(Max) x 6.6(Max) x 3.42(Max)mm
Customers Who Bought 74F112PC Also Bought
The 74F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on S#
prevents clocking and forces Q or Q# HIGH, respectively. Simultaneous LOW signals on S#
force both Q and Q# HIGH
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