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PRODUCT INFO
74F112PC by FAIRCHILD
Image is representational - see manufacturer’s specifications
FAIRCHILD

74F112PC

Fairchild

Flip Flop JK-Type Neg-Edge 2-Element 16-Pin PDIP W Rail

PRICING per each  AVAILABILITY real time   
1-24 :$0.42
25-99 :$0.39
100-249 :$0.35
250-499 :$0.35
500-999 :$0.31
1,000-2,499 :$0.30
2,500 + :$0.29
1,671 can ship Monday
In our stock 
Ships From: Phoenix, AZ
RESOURCES
SPECS
Supplier: Fairchild
Part No: 74F112PC
RoHS: Yes
Supplier Standard Pack: This information is provided for customers who prefer to buy in multiples of the Manufacturer’s Standard Package quantity. <b>Minimum Order Quantities</b> and <b>Required Order Multiples</b> are presented with our price and availability information. 500
Maximum Low Level Output Current: 20 mA
Logic Function: JK-Type
Minimum Operating Supply Voltage: 4.5 V
Number of Channels per Chip: 2
Output Type: N/A
Family: 74F112
Polarity: Inverting/Non-Inverting
Supplier_Package: PDIP W
Packaging: Rail
Logic Family: F
Pin_Count: 16
Mounting: Through Hole
Maximum High Level Output Current: -1 mA
Number of Elements per Chip: 2
Maximum Operating Supply Voltage: 5.5 V
Typical Operating Supply Voltage: 5 V
Operating Temperature: 0 to 70 °C
Dimension: 19.68(Max) x 6.6(Max) x 3.42(Max) mm
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DESCRIPTION
The 74F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on S#D or C#D prevents clocking and forces Q or Q# HIGH, respectively. Simultaneous LOW signals on S#D and C#D force both Q and Q# HIGH
COMMUNITY FORUM
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PART CLASSIFICATION DATA
HTS: 8542390000
ECCN: EAR99
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