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PRODUCT INFO
74ACT109PC by FAIRCHILD
Image is representational - see manufacturer’s specifications
FAIRCHILD

74ACT109PC

Fairchild

Flip Flop JK# -Type Pos-Edge 2-Element 16-Pin PDIP W Rail

PRICING per each  AVAILABILITY real time   
1-24 :$0.56
25-99 :$0.53
100-249 :$0.48
250-499 :$0.46
500-999 :$0.42
1,000-2,499 :$0.40
2,500 + :$0.39
42 can ship Monday
In our stock 
Ships From: Phoenix, AZ
RESOURCES
SPECS
Supplier: Fairchild
Part No: 74ACT109PC
RoHS: Yes
Supplier Standard Pack: This information is provided for customers who prefer to buy in multiples of the Manufacturer’s Standard Package quantity. <b>Minimum Order Quantities</b> and <b>Required Order Multiples</b> are presented with our price and availability information. 500
Maximum Low Level Output Current: 24 mA
Logic Function: JK# -Type
Minimum Operating Supply Voltage: 4.5 V
Number of Channels per Chip: 2
Output Type: N/A
Family: 74ACT109
Polarity: Inverting/Non-Inverting
Supplier_Package: PDIP W
Packaging: Rail
Logic Family: ACT
Pin_Count: 16
Mounting: Through Hole
Maximum High Level Output Current: -24 mA
Number of Elements per Chip: 2
Maximum Operating Supply Voltage: 5.5 V
Typical Operating Supply Voltage: 5 V
Operating Temperature: -40 to 85 °C
Dimension: 19.68(Max) x 6.6(Max) x 3.42(Max) mm
Customers Who Bought 74ACT109PC Also Bought
DESCRIPTION

The AC/ACT109 consists of two high-speed completely independent transition clocked JK# flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK# design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K# inputs together.

Asynchronous Inputs:

LOW input to S#D (Set) sets Q to HIGH level

LOW input to C#D (Clear) sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on C#D and S#D makes both Q and Q HIGH#

Product Highlights

  • ICC reduced by 50%
  • Outputs source/sink 24 mA
  • ACT109 has TTL-compatible inputs
COMMUNITY FORUM
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PART CLASSIFICATION DATA
HTS: 8542390000
ECCN: EAR99
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