| • | Dual independent UARTs |
| • | Capable of running all existing 16450 and PC16550D software |
| • | After reset, all registers are identical to the 16450 register set |
| • | Read and write cycle times of 84 ns |
| • | In the FIFO mode transmitter and receiver are each buffered with 16-byte FIFOs to reduce the number of interrupts presented to the CPU |
| • | Holding and shift registers in the 16450 Mode eliminate the need for precise synchronization between the CPU and serial data |
| • | Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data |
| • | Independently controlled transmit, receive, line status, and data set interrupts |
| • | Programmable baud generators divide any input clock by 1 to (216 - 1) and generate the 16 × clock |
| • | MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD) |
| • | Fully programmable serial-interface characteristics: |
| • | 5-, 6-, 7-, or 8-bit characters |
| • | Even, odd, or no-parity bit generation and detection |
| • | 1-, 1½-, or 2-stop bit generation |
| • | Baud generation (DC to 1.5M baud) with 16 × clock |
| • | False start bit detection |
| • | Complete status reporting capabilities |
| • | TRI-STATE® TTL drive for the data and control buses |
| • | Line break generation and detection |
| • | Internal diagnostic capabilities: |
| • | Loopback controls for communications link fault isolation |
| • | Break, parity, overrun, framing error simulation |
| • | Full prioritized interrupt system controls |
*Can also be reset to 16450 Mode under software control.†Note: This part is patented.