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Standard & Specialty Logic
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Latch Transparent 3-ST 8-CH D-Type 20-Pin PDIP W Rail
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Maximum Low Level Output Current:
Minimum Operating Supply Voltage:
Number of Channels per Chip:
Maximum High Level Output Current:
Maximum Operating Supply Voltage:
Typical Operating Supply Voltage:
-40 to 85 °C
26.92(Max) x 7.11(Max) x 3.43(Max)mm
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The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system.
When the LATCH ENABLE input is HIGH, the Q outputs will follow the D inputs. When the LATCH ENABLE goes LOW, data at the D inputs will be retained at the outputs until LATCH ENABLE returns HIGH again. When a high logic level is applied to the OUTPUT CONTROL input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family
Typical propagation delay: 18 ns
Wide operating voltage range: 2 to 6 volts
Low input current: 1 µA maximum
Low quiescent current: 80 µA maximum (74 Series)
Output drive capability: 15 LS-TTL loads
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